1. Field of the Invention
The present invention relates to an electric power semiconductor device used in, for example, a motor control or an inverter, and more particularly relates to an electric power semiconductor device in which a heat release characteristic is improved, facilitating connection to an outer conducting plate, and realizing miniaturization and implementation of high capacity.
2. Description of the Prior Art
In general, an electric power semiconductor device (also, referred to as “a semiconductor power module” hereinafter) converts an input direct current to an alternate current output of certain frequency using a semiconductor, which is used in a motor control, an inverter according to various kinds of usage, an uninterruptible power source (UPS) or the like.
Conventionally, as a semiconductor device having a plurality of IC chips mounted on a package, there is disclosed a device in which a relay electrode plate portion is provided in a middle section of the device and IC chips are electrically connected to each other and to the outside through the relay electrode plate portion (referring to e.g. Japanese Patent Laid-Open Publication No. 8-264596.
In addition, there is disclosed a constitution in which an electrode plate is symmetric about a center line of the electrode plate on a substrate (referring to e.g. Japanese Patent Laid-Open Publication No. 2000-323647.
FIGS. 3 and 4 are a plan view and a partially side sectional view, respectively showing a semiconductor power module 10 described in the Japanese Patent Laid-Open Publication No. 2003-133515 which was suggested by the present inventors. As shown in FIGS. 3 and 4, reference numerals 2a and 2b designate a pair of right and left dye pad insulating substrates on which a plurality of IC chips are mounted, reference numerals 3a and 3b designate circuit patterns formed on the dye pad insulating substrates, reference numerals 4a and 4b designate semiconductor chips mounted on the circuit patterns 3a and 3b, reference numeral 6 designates a multilayer electrode plate assembly. The multilayer electrode plate assembly 6 comprises three layered electrode terminal plates 6a, 6b and 6c, and insulating layers 7a, 7b and 7c interposed between the electrode terminal plates 6a, 6b and 6c, respectively. Reference numeral 11 designates a metal base for cooling and reference numerals 21a, 21b, 22a and 22b designate metal wires.
As shown in FIGS. 3 and 4, the insulating substrates 2a and 2b are fixed to the metal base 11 for cooling and the circuit patterns 3a and 3b are fixed to the surfaces of the insulating substrates. The plural semiconductor chips 4a and 4b are connected onto the circuit patterns 3a and 3b by soldering or the like. The semiconductor chips 4a and 4b are arranged along a pair of opposite side lines of the quadrate metal base 11 for cooling which extends in a longitudinal direction in the drawing. The multilayer electrode plate assembly 6 is disposed between the two arrays of the semiconductor chips 4a and 4b along the above pair of opposite side lines. The semiconductor chips 4a and 4b are electrically connected to each other through the three layered electrode terminal plates 6a, 6b and 6c formed on the die pad insulating substrates.
FIG. 4 is a side view showing a structure of the multilayer electrode plate assembly 6 and a state of the connection between the semiconductor chips 4a and 4b. Each terminal of the semiconductor chips 4a and 4b and circuit patterns 3a and 3b are connected to the three electrode terminal plates 6a, 6b and 6c. More specifically, the wires 21a and 21b connect the electrode terminal plates 6a and 6b to the semiconductor chips 4a and 4b, respectively, by wire bonding, and the wires 22a and 22b connect the electrode terminal plates 6b and 6c to the semiconductor chips 3a and 3b, respectively, by wire bonding.
When the semiconductor module is assembled, in the first step, the wires 22a and 22b are provided so that the electrode terminal plates 6b and 6c are electrically connected to the semiconductor chips 3a and 3b through the wires 22a and 22b, respectively. Then, the wires 21a and 21b are provided so that the electrode terminal plates 6a and 6b are connected to the semiconductor chips 4a and 4b through the wires 21a and 21b, respectively. The electrode terminal plates 6a, 6b and 6c form a laminated structure together with the insulating layers 7a, 7b and 7c alternately disposed under the electrode terminal plates 6a, 6b and 6c which are insulated by the insulating layers 7a, 7b and 7c to each other.
The electrode terminal plates 6a, 6b and 6c extend outside a resin case (not shown) and form an external connecting main circuit terminals such as a P terminal, an N terminal, an alternate current terminal or the like (not shown) on the semiconductor power module 10, respectively. In addition, an internal space surrounded by the resin case is filled with a filling material such as silicon gel.
In this conventional semiconductor power module 10 having such an inner structure, since the multilayer electrode plate assembly 6 has the laminated structure, mutual inductance between the electrode terminal plates 6a, 6b and 6c is reduced as much as possible, and suppressing damages which may be caused when the semiconductor power module 10 is started or shut off, or caused by reverse inductive electromotive force when a voltage is varied.
However, in the above conventional semiconductor power module, as shown in FIG. 4, since the wires 21a and 21b and the wires 22a and 22b are adjacently provided, there is a limit in number of the wires which can be provided in a predetermined region. As a result, there arise a problem such that current flowing in one wire is increased and heat is generated in the wire or a voltage drop is caused in the wire.
Furthermore, in the case where a large-sized semiconductor power module is assembled, the number of wires is further increased and the time necessary for the wiring is increased, which reduces production efficiency to be a problem.